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rev: 1.00 10/2001 1/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. nobl is a trademark of cypress semiconductor corp.. ntram is a trademark of samsung electronics co.. zbt is a trademark of integ rated device technology, inc. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) 2m x 18, 1m x 36 , 512k x 72 36mb sync nbt srams 250 mhz ? 133mhz 2.5 v or 3.3 v v dd 2.5 v or 3.3 v i/o 119- and 209-pin bga commercial temp industrial temp features ? nbt (no bus turn around) functionality allows zero wait read-write-read bus utilization; fully pin-compatible with both pipelined and flow through ntram?, nobl? and zbt? srams ? ft pin for user-configurable flow through or pipeline operation ? ieee 1149.1 jtag-compatible boundary scan ? zq mode pin for user-selectable high /low output drive ? 2.5 v or 3.3 v +10%/?5% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleaved burst mode ? byte write ( bw ) and/or global write ( gw ) operation ? internal self-timed write cycle ? automatic power-down for portable applications ? jedec-standard 119- and 209-bump bga package functional description applications the gs 8 324z 18/36 /72 is a 37,748,736 -bit high performance 2-die synchronous sram module with a 2-bit burst address counter. although of a type originally developed for level 2 cache applications supporting high performance cpus, the device now finds application in synchronous sram applications, ranging from dsp main store to networking chip set support. controls addresses, data i/os, chip enable ( e1 ), address burst control inputs ( adsp , adsc , adv ), and write control inputs ( bx , bw , gw ) are synchronous and are controlled by a positive-edge- triggered clock input (ck). output enable ( g ) and power down control (zz) are asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subsequent burst addresses are generated internally and are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order ( lbo ) input. the burst function need not be used. new addresses can be loaded on every cycle with no degradation of chip performance. flow through/pipeline reads the function of the data output register can be controlled by the user via the ft mode . holding the ft mode pin low places the ram in flow through mode, causing output data to bypass the data output register. holding ft high places the ram in pipeline mode, activating the rising-edge-triggered data output register. byte write and global write byte write operation is performed by using byte write enable ( bw ) input combined with one or more individual byte write signals ( bx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write control inputs. flxdrive? the zq pin allows selection between high drive strength (zq low) for multi-drop bus applications and normal drive strength (zq floating or high) point-to-point applications. see the output driver characteristics chart for details. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. core and interface voltages the gs 8 324z 18/36 /72 operates on a 2.5 v or 3.3 v power supply. all input are 3.3 v and 2.5 v compatible. separate output power ( v ddq ) pins are used to decouple output noise from the internal circuits and are 3.3 v and 2.5 v compatible. -250 -225 -200 -166 -150 -133 unit pipeline 3-1-1-1 t kq tcycle 2.3 4.0 2.5 4.4 3.0 5.0 3.5 6.0 3.8 6.6 4.0 7.5 ns ns 3.3 v curr (x18) curr (x36) curr (x72) 365 560 660 335 510 600 305 460 540 265 400 460 245 370 430 215 330 380 ma ma ma 2.5 v curr (x18) curr (x36) curr (x72) 360 550 640 330 500 590 305 460 530 260 390 450 240 360 420 215 330 370 ma ma ma flow through 2-1-1-1 t kq tcycle 6.0 7.0 6.5 7.5 7.5 8.5 8.5 10 10 10 11 15 ns ns 3.3 v curr (x18) curr (x36) curr (x72) 235 300 350 230 300 350 210 270 300 200 270 300 195 270 300 150 200 220 ma ma ma 2.5 v curr (x18) curr (x36) curr (x72) 235 300 340 230 300 340 210 270 300 200 270 300 195 270 300 145 190 220 ma ma ma
rev: 1.00 10/2001 2/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) gs8324z72b pad out 209-bump bga?top view 1 2 3 4 5 6 7 8 9 10 11 a dq g5 dq g1 a13 e2 a14 adv a15 e3 a17 dq b1 dq b5 a b dq g6 dq g2 b c b g nc w a16 b b b f dq b2 dq b6 b c dq g7 dq g3 b h b d nc e1 nc b e b a dq b3 dq b7 c d dq g8 dq g4 v ss nc nc g nc nc v ss dq b4 dq b8 d e dqp g9 dqp c9 v ddq v ddq v dd v dd v dd v ddq v ddq dqp f9 dqp b9 e f dq c4 dq c8 v ss v ss v ss zq v ss v ss v ss dq f8 dq f4 f g dq c3 dq c7 v ddq v ddq v dd mch v dd v ddq v ddq dq f7 dq f3 g h dq c2 dq c6 v ss v ss v ss mcl v ss v ss v ss dq f6 dq f2 h j dq c1 dq c5 v ddq v ddq v dd mch v dd v ddq v ddq dq f5 dq f1 j k nc nc ck nc v ss mcl v ss nc nc nc nc k l dq h1 dq h5 v ddq v ddq v dd ft v dd v ddq v ddq dq a5 dq a1 l m dq h2 dq h6 v ss v ss v ss mcl v ss v ss v ss dq a6 dq a2 m n dq h3 dq h7 v ddq v ddq v dd mch v dd v ddq v ddq dq a7 dq a3 n p dq h4 dq h8 v ss v ss v ss zz v ss v ss v ss dq a8 dq a4 p r dqp d9 dqp h9 v ddq v ddq v dd v dd v dd v ddq v ddq dqp a9 dqp e9 r t dq d8 dq d4 v ss nc nc lbo pe nc v ss dq e4 dq e8 t u dq d7 dq d3 nc a12 nc a11 a18 a10 nc dq e3 dq e7 u v dq d6 dq d2 a9 a8 a7 a1 a6 a5 a4 dq e2 dq e6 v w dq d5 dq d1 tms tdi a3 a0 a2 tdo tck dq e1 dq e5 w 11 x 19 bump bga?14 x 22 mm 2 body?1 mm bump pitch
rev: 1.00 10/2001 3/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) gs8324z36c pad out 209-bump bga?top view 1 2 3 4 5 6 7 8 9 10 11 a nc nc a13 e2 a14 adv a15 e3 a17 dq b1 dq b5 a b nc nc b c nc a19 w a16 b b nc dq b2 dq b6 b c nc nc nc b d nc e1 nc nc b a dq b3 dq b7 c d nc nc v ss nc nc g nc nc v ss dq b4 dq b8 d e nc dqp c9 v ddq v ddq v dd v dd v dd v ddq v ddq nc dqp b9 e f dq c4 dq c8 v ss v ss v ss zq v ss v ss v ss nc nc f g dq c3 dq c7 v ddq v ddq v dd mch v dd v ddq v ddq nc nc g h dq c2 dq c6 v ss v ss v ss mcl v ss v ss v ss nc nc h j dq c1 dq c5 v ddq v ddq v dd mch v dd v ddq v ddq nc nc j k nc nc ck nc v ss mcl v ss nc nc nc nc k l nc nc v ddq v ddq v dd ft v dd v ddq v ddq dq a5 dq a1 l m nc nc v ss v ss v ss mcl v ss v ss v ss dq a6 dq a2 m n nc nc v ddq v ddq v dd mch v dd v ddq v ddq dq a7 dq a3 n p nc nc v ss v ss v ss zz v ss v ss v ss dq a8 dq a4 p r dqp d9 nc v ddq v ddq v dd v dd v dd v ddq v ddq dqp a9 nc r t dq d8 dq d4 v ss nc nc lbo pe nc v ss nc nc t u dq d7 dq d3 nc a12 nc a11 a18 a10 nc nc nc u v dq d6 dq d2 a9 a8 a7 a1 a6 a5 a4 nc nc v w dq d5 dq d1 tms tdi a3 a0 a2 tdo tck nc nc w 11 x 19 bump bga?14 x 22 mm 2 body?1 mm bump pitch
rev: 1.00 10/2001 4/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) gs8324z18c pad out 209-bump bga?top view 1 2 3 4 5 6 7 8 9 10 11 a nc nc a13 vdd a14 adv a15 vss a17 nc nc a b nc nc b b nc a19 w a16 nc nc nc nc b c nc nc nc nc nc e1 a20 nc b a nc nc c d nc nc v ss nc nc g nc nc v ss nc nc d e nc dqp b9 v ddq v ddq v dd v dd v dd v ddq v ddq nc nc e f dq b4 dq b8 v ss v ss v ss zq v ss v ss v ss nc nc f g dq b3 dq b7 v ddq v ddq v dd mch v dd v ddq v ddq nc nc g h dq b2 dq b6 v ss v ss v ss mcl v ss v ss v ss nc nc h j dq b1 dq b5 v ddq v ddq v dd mch v dd v ddq v ddq nc nc j k nc nc ck nc v ss mcl v ss nc nc nc nc k l nc nc v ddq v ddq v dd ft v dd v ddq v ddq dq a5 dq a1 l m nc nc v ss v ss v ss mcl v ss v ss v ss dq a6 dq a2 m n nc nc v ddq v ddq v dd vdd v dd v ddq v ddq dq a7 dq a3 n p nc nc v ss v ss v ss zz v ss v ss v ss dq a8 dq a4 p r nc nc v ddq v ddq v dd v dd v dd v ddq v ddq dqp a9 nc r t nc nc v ss nc nc lbo pe nc v ss nc nc t u nc nc nc a12 nc a11 a18 a10 nc nc nc u v nc nc a9 a8 a7 a1 a6 a5 a4 nc nc v w nc nc tms tdi a3 a0 a2 tdo tck nc nc w 11 x 19 bump bga?14 x 22 mm 2 body?1 mm bump pitch
rev: 1.00 10/2001 5/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) gs8324z18/36/72 209-bump bga pin description pin location symbol type description w6, v6 a 0 , a 1 i address field lsbs and address counter preset inputs. w7, w5, v9, v8, v7, v5, v4, v3, u8, u6, u4, a3, a5, a7, b7, a9, u7 an i address inputs b5 a 19 i address inputs (x36/x18 versions) c7 a 20 i address inputs (x18 version) l11, m11, n11, p11, l10, m10, n10, p10, r10 a10, b10, c10, d10, a11, b11, c11, d11, e11 j1, h1, g1, f1, j2, h2, g2, f2, e2 w2, v2, u2, t2, w1, v1, u1, t1, r1 w10, v10, u10, t10, w11, v11, u11, t11, r11 j11, h11, g11, f11, j10, h10, g10, f10, e10 a2, b2, c2, d2, a1, b1, c1, d1, e1 l1, m1, n1, p1, l2, m2, n2, p2, r2 dq a1 ? dq a9 dq b1 ? dq b9 dq c1 ? dq c9 dq d1 ? dq d9 dq e1 ? dq e9 dq f1 ? dq f9 dq g1 ? dq g9 dq h1 ? dq h9 i/o data input and output pins (x72 version) l11, m11, n11, p11, l10, m10, n10, p10, r10 a10, b10, c10, d10, a11, b11, c11, d11, e11 j1, h1, g1, f1, j2, h2, g2, f2, e2 w2, v2, u2, t2, w1, v1, u1, t1, r1 dq a1 ? dq a9 dq b1 ? dq b9 dq c1 ? dq c9 dq d1 ? dq d9 i/o data input and output pins (x36 version) l11, m11, n11, p11, l10, m10, n10, p10, r10 j1, h1, g1, f1, j2, h2, g2, f2, e2 dq a1 ? dq a9 dq b1 ? dq b9 i/o data input and output pins (x18 version) c9, b8 b a , b b i byte write enable for dq a , dq b i/os; active low b3, c4 b c , b d i byte write enable for dq c , dq d i/os; active low (x72/x36 versions) c8, b9, b4, c3 b e , b f , b g , b h i byte write enable for dq e , dq f , dq g , dq h i/os; active low (x72 version) b5 nc ? no connect (x72 version) c7 nc ? no connect (x72/x36 versions) w10, v10, u10, t10, w11, v11, u11, t11, r11 j11, h11, g11, f11, j10, h10, g10, f10, e10 a2, b2, c2, d2, a1, b1, c1, d1, e1 l1, m1, n1, p1, l2, m2, n2, p2, r2, c8, b9, b4, c3 nc ? no connect (x36/x18 versions) b3, c4 nc ? no connect (x18 version) c5, d4, d5, d7, d8, k1, k2, k4, k8, k9, k10, k11, t4, t5, t7, t8, u3, u5, u9 nc ? no connect k3 ck i clock input signal; active high c6 e 1 i chip enable; active low a8 e 3 i chip enable; active low (x72/x36 versions) a4 e 2 i chip enable; active high (x72/x36 versions) d6 g i output enable; active low a6 adv i burst address counter advance enable
rev: 1.00 10/2001 6/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) p6 zz i sleep mode control; active high l6 ft i flow through or pipeline mode; active low t6 lbo i linear burst order mode; active low g6, j6 mch i must connect high n6 mch i must connect high (x72 and x36 versions) h6, j6, k6, m6 mcl must connect low a8, n6 mcl must connect low (x18 version) b6 w i write enable; active low t7 pe i parity bit enable; active low (high = x16/32 mode, low = x18/36 mode) f6 zq i flxdrive output impedance control (low = low impedance [high drive], high = high impedance [low drive]) w3 tms i scan test mode select w4 tdi i scan test data in w8 tdo o scan test data out w9 tck i scan test clock a4, n6 v dd i core power supply (x18 version) e5, e6, e7, g5, g7, j5, j7, l5, l7, n5, n7, r5, r6, r7 v dd i core power supply d3, d9, f3, f4, f5, f7, f8, f9, h3, h4, h5, h7, h8, h9, k5, k7, m3, m4, m5, m7, m8, m9, p3, p4, p5, p7, p8, p9, t3, t9 v ss i i/o and core ground e3, e4, e8, e9, g3, g4, g8, g9, j3, j4, j8, j9, l3, l4, l8, l9, n3, n4, n8, n9, r3, r4, r8, r9 v ddq i output driver power supply gs8324z18/36/72 209-bump bga pin description pin location symbol type description
rev: 1.00 10/2001 7/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) gs8324z36b pad out 119-bump bga?top view 1 2 3 4 5 6 7 a v ddq a6 a7 a18 a8 a9 v ddq a b nc e2 a4 adv a15 e3 nc b c nc a5 a3 v dd a14 a16 nc c d dqc dqpc v ss zq v ss dqpb dqb d e dqc dqc v ss e1 v ss dqb dqb e f v ddq dqc v ss g v ss dqb v ddq f g dqc dqc b c a17 b b dqb dqb g h dqc dqc v ss w v ss dqb dqb h j v ddq v dd nc v dd nc v dd v ddq j k dqd dqd v ss ck v ss dqa dqa k l dqd dqd b d nc b a dqa dqa l m v ddq dqd v ss cke v ss dqa v ddq m n dqd dqd v ss a1 v ss dqa dqa n p dqd dqpd v ss a0 v ss dqpa dqa p r nc a2 lbo v dd ft a13 pe r t nc nc a10 a11 a12 a19 zz t u v ddq tms tdi tck tdo nc v ddq u 7 x 17 bump bga?14 x 22 mm 2 body?1.27 mm bump pitch
rev: 1.00 10/2001 8/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) gs8324z18b pad out 119-bump bga?top view 1 2 3 4 5 6 7 a v ddq a6 a7 a18 a8 a9 v ddq a b nc vdd a4 adv a15 vss nc b c nc a5 a3 v dd a14 a16 nc c d dqb nc v ss zq v ss dqpa nc d e nc dqb v ss e1 v ss nc dqa e f v ddq nc v ss g v ss dqa v ddq f g nc dqb b b a17 nc nc dqa g h dqb nc v ss w v ss dqa nc h j v ddq v dd nc v dd nc v dd v ddq j k nc dqb v ss ck v ss nc dqa k l dqb nc nc vdd b a dqa nc l m v ddq dqb v ss cke v ss nc v ddq m n dqb nc v ss a1 v ss dqa nc n p nc dqpb v ss a0 v ss nc dqa p r nc a2 lbo v dd ft a13 pe r t nc a10 a11 a20 a12 a19 zz t u v ddq tms tdi tck tdo nc v ddq u 7 x 17 bump bga?14 x 22 mm 2 body?1.27 mm bump pitch
rev: 1.00 10/2001 9/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) gs8324z18/36 119-bump bga pin description pin location symbol type description p4, n4 a 0 , a 1 i address field lsbs and address counter preset inputs r2, c3, b3, c2, a2, a3, a5, a6, t3, t5, r6, c5, b5, c6, g4, a4 an i address inputs t4, t6 an address input (x36 version) t2 nc ? no connect (x36 version) t2, t6, t4 an i address input (x18 version) k7, l7, n7, p7, k6, l6, m6, n6 h7, g7, e7, d7, h6, g6, f6, e6 h1, g1, e1, d1, h2, g2, f2, e2 k1, l1, n1, p1, k2, l2, m2, n2 dq a1 ?dq a8 dq b1 ?dq b8 dq c1 ?dq c8 dq d1 ?dq d8 i/o data input and output pins. (x36 version) p6, d6, d2, p2 dq a9 , dq b9 , dq c9 , dq d9 i/o data input and output pins. (x36 version) l5, g5, g3, l3 b a , b b , b c , b d i byte write enable for dq a , dq b , dq c , dq d i/os; active low (x36 version) p7, n6, l6, k7, h6, g7, f6, e7, d6 d1, e2, g2, h1, k2, l1, m2, n1, p2 dq a1 ?dq a9 dq b1 ?dq b9 i/o data input and output pins (x18 version) l5, g3 b a , b b i byte write enable for dq a , dq b i/os; active low (x18 version) b1, c1, r1, t1, u6, b7, c7, j3, j5 nc ? no connect p6, n7, m6, l7, k6, h7, g6, e6, d7, d2, e1, f2, g1, h2, k1, l2, n2, p1, g5, l3 nc ? no connect (x18 version) l4 nc ? no connect (x36 version) k4 ck i clock input signal; active high m4 cke i clock enable; active low h4 w i write enable; active low e4 e 1 i chip enable; active low b6 e 3 i chip enable; active low (x36 version) b2 e 2 i chip enable; active high (x36 version) f4 g i output enable; active low b4 adv i burst address counter advance enable t7 zz i sleep mode control; active high r5 ft i flow through or pipeline mode; active low r3 lbo i linear burst order mode; active low d4 zq i flxdrive output impedance control (low = low impedance [high drive], high = high impedance [low drive]) r7 pe i parity bit enable; active low u2 tms i scan test mode select u3 tdi i scan test data in
rev: 1.00 10/2001 10/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) u5 tdo o scan test data out u4 tck i scan test clock j2, c4, j4, r4, j6 v dd i core power supply b2, l4 v dd i core power supply (x18 version) d3, e3, f3, h3, k3, m3, n3, p3, d5, e5, f5, h5, k5, m5, n5, p5 v ss i i/o and core ground b6 v ss i i/o and core ground (x18 version) a1, f1, j1, m1, u1, a7, f7, j7, m7, u7 v ddq i output driver power supply gs8324z18/36 119-bump bga pin description pin location symbol type description
rev: 1.00 10/2001 11/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) gs 8324z 18/36/72 block diagram a1 a0 a0 a1 d0 d1 q1 q0 counter load d q d q register register d q register d q register d q register d q register d q register d q register d q r e g i s t e r d q r e g i s t e r a0?an lbo adv ck adsc adsp gw bw e 1 ft g zz power down control memory array 36 36 4 a q d dqx0?dqx9 36 36 note: only x36 version shown for simplicity. 36 36 b a b b b c b d
rev: 1.00 10/2001 12/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) inputs tdo tdi tdo tdi 18 i/os die a x18 16mb die b x18 16mb gs8324 z 18 die layout inputs tdo tdi tdo tdi 18 i/os 18 i/os die a x18 16mb die b x18 16mb gs8324 z 36 die layout inputs tdo tdi tdo tdi 36 i/os 36 i/os die a x36 32mb die b x36 32mb gs8324 z 72 die layout
rev: 1.00 10/2001 13/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) functional details clocking deassertion of the clock enable ( cke ) input blocks the clock input from reaching the ram's internal circuits. it may be used to suspend ram operations. failure to observe clock enable set-up or hold requirements will result in erratic operation. pipeline mode read and write operations all inputs (with the exception of output enable, linear burst order and sleep) are synchronized to rising clock edges. single cy cle read and write operations must be initiated with the advance/ load pin (adv) held low, in order to load the new address. device activation is accomplished by asserting all three of the chip enable inputs ( e 1 , e 2, and e 3 ). deassertion of any one of the enable inputs will deactivate the device. read operation is initiated when the following conditions are satisfied at the rising edge of clock: cke is asserted low, all three chip enables ( e 1 , e 2, and e 3 ) are active, the write enable input signals w is deasserted high, and adv is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the con trol logic determines that a read access is in progress and allows the requested data to propagate to the input of the output registe r. at the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. write operation occurs when the ram is selected, cke is active, and the write input is sampled low at the rising edge of clock. the byte write enable inputs ( b a , b b , b c, and b d ) determine which bytes will be written. all or none may be activated. a write cycle with no byte write inputs active is a no-op cycle. the pipelined nbt sram provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). at the first rising edge of clock, enable, write, byte write(s), and address are registered. the data in associated with that addre ss is required at the third rising edge of clock. flow through mode read and write operations operation of the ram in flow through mode is very similar to operations in pipeline mode. activation of a read cycle and the use of the burst address counter is identical. in flow through mode the device may begin driving out new data immediately after new address are clocked into the ram, rather than holding new data until the following (second) clock edge. therefore, in flow through mode the read pipeline is one cycle shorter than in pipeline mode. write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving t he ability to turn the bus from reads to writes without inserting any dead cycles. while the pipelined nbt rams implement a double late write protocol in flow through mode a single late write protocol mode is observed. therefore, in flow through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock. function w b a b b b c b d read h x x x x write byte ?a? l l h h h write byte ?b? l h l h h write byte ?c? l h h l h write byte ?d? l h h h l write all bytes l l l l l write abort/nop l h h h h
rev: 1.00 10/2001 14/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) byte write truth table notes: 1. all byte outputs are active in read cycles regardless of the state of byte write enable inputs. 2. byte write enable inputs b a , b b , b c , and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/os remain high-z during all write operations regardless of the state of byte write enable inputs. 4. bytes ? c ? and ? d ? are only available on the x36 version. function gw bw b a b b b c b d notes read h h x x x x 1 read h l h h h h 1 write byte a h l l h h h 2, 3 write byte b h l h l h h 2, 3 write byte c h l h h l h 2, 3, 4 write byte d h l h h h l 2, 3, 4 write all bytes h l l l l l 2, 3, 4 write all bytes l x x x x x
rev: 1.00 10/2001 15/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) synchronous truth table (x72 and x36 209-bump bga) operation type address e 1 e 2 e 3 zz adv w bx g cke ck dq notes deselect cycle, power down d none h x x l l x x x l l-h high-z deselect cycle, power down d none x x h l l x x x l l-h high-z deselect cycle, power down d none x l x l l x x x l l-h high-z deselect cycle, continue d none x x x l h x x x l l-h high-z 1 read cycle, begin burst r external l h l l l h x l l l-h q read cycle, continue burst b next x x x l h x x l l l-h q 1,10 nop/read, begin burst r external l h l l l h x h l l-h high-z 2 dummy read, continue burst b next x x x l h x x h l l-h high-z 1,2,10 write cycle, begin burst w external l h l l l l l x l l-h d 3 write cycle, continue burst b next x x x l h x l x l l-h d 1,3,10 nop/write abort, begin burst w none l h l l l l h x l l-h high-z 2,3 write abort, continue burst b next x x x l h x h x l l-h high-z 1,2,3,10 clock edge ignore, stall current x x x l x x x x h l-h - 4 sleep mode none x x x h x x x x x x high-z notes: 1. continue burst cycles, whether read or write, use the same control inputs. a deselect continue cycle can only be entered into if a deselect cycle is executed first. 2. dummy read and write abort can be considered nops because the sram performs no operation. a write abort occurs when the w pin is sampled low but no byte write pins are active, so no write operation is performed. 3. g can be wired low to minimize the number of control signals provided to the sram. output drivers will automatically turn off dur ing write cycles. 4. if cke high occurs during a pipelined read cycle, the dq bus will remain active (low z). if cke high occurs during a write cycle, the bus will remain in high z. 5. x = don?t care; h = logic high; l = logic low; bx = high = all byte write signals are high; bx = low = one or more byte/write signals are low 6. all inputs, except g and zz must meet setup and hold times of rising clock edge. 7. wait states can be inserted by setting cke high. 8. this device contains circuitry that ensures all outputs are in high z during power-up. 9. a 2-bit burst counter is incorporated. 10. the address counter is incriminated for all burst continue cycles.
rev: 1.00 10/2001 16/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) synchronous truth table (x18 209-bump bga and x36/x18 119-bump bga) operation type address e 1 zz adv w bx g cke ck dq notes deselect cycle, power down d none h l l x x x l l-h high-z deselect cycle, power down d none x l l x x x l l-h high-z deselect cycle, power down d none x l l x x x l l-h high-z deselect cycle, continue d none x l h x x x l l-h high-z 1 read cycle, begin burst r external l l l h x l l l-h q read cycle, continue burst b next x l h x x l l l-h q 1,10 nop/read, begin burst r external l l l h x h l l-h high-z 2 dummy read, continue burst b next x l h x x h l l-h high-z 1,2,10 write cycle, begin burst w external l l l l l x l l-h d 3 write cycle, continue burst b next x l h x l x l l-h d 1,3,10 nop/write abort, begin burst w none l l l l h x l l-h high-z 2,3 write abort, continue burst b next x l h x h x l l-h high-z 1,2,3,10 clock edge ignore, stall current x l x x x x h l-h - 4 sleep mode none x h x x x x x x high-z notes: 1. continue burst cycles, whether read or write, use the same control inputs. a deselect continue cycle can only be entered into if a deselect cycle is executed first. 2. dummy read and write abort can be considered nops because the sram performs no operation. a write abort occurs when the w pin is sampled low but no byte write pins are active, so no write operation is performed. 3. g can be wired low to minimize the number of control signals provided to the sram. output drivers will automatically turn off during write cycles. 4. if cke high occurs during a pipelined read cycle, the dq bus will remain active (low z). if cke high occurs during a write cycle, the bus will remain in high z. 5. x = don?t care; h = logic high; l = logic low; bx = high = all byte write signals are high; bx = low = one or more byte/ write signals are low 6. all inputs, except g and zz must meet setup and hold times of rising clock edge. 7. wait states can be inserted by setting cke high. 8. this device contains circuitry that ensures all outputs are in high z during power-up. 9. a 2-bit burst counter is incorporated. 10. the address counter is incriminated for all burst continue cycles.
rev: 1.00 10/2001 17/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) deselect new read new write burst read burst write w r b r b w d d b b w r d b w r d d pipelined and flow through read write control state diagram current state (n) next state (n+1) transition ? input command code key notes 1. the hold command ( cke low) is not shown because it prevents any state change. 2. w, r, b , and d represent input command codes as indicated in the synchronous truth table. clock (ck) command current state next state ? n n+1 n+2 n+3 ? ? ? current state and next state definition for pipelined and flow through read/write control state diagram w r
rev: 1.00 10/2001 18/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) intermediate intermediate intermediate intermediate intermediate intermediate high z (data in) data out (q valid) high z b w b r b d r w r w d d pipeline mode data i/o state diagram current state (n) next state (n+2) transition ? input command code key transition intermediate state (n+1) notes 1. the hold command ( cke low) is not shown because it prevents any state change. 2. w, r, b , and d represent input command codes as indicated in the truth tables. clock (ck) command current state intermediate ? n n+1 n+2 n+3 ? ? ? current state and next state definition for pipeline mode data i/o state diagram next state state
rev: 1.00 10/2001 19/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+1) transition ? input command code key notes 1. the hold command ( cke low) is not shown because it prevents any state change. 2. w, r, b , and d represent input command codes as indicated in the truth tables. flow through mode data i/o state diagram clock (ck) command current state next state ? n n+1 n+2 n+3 ? ? ? current state and next state definition for: pipeline and flow through read write control state diagram
rev: 1.00 10/2001 20/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) burst cycles although nbt rams are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. nbt srams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the counter generated address to read or write the sram. the starting address for the first cycle in a burst cycle series is loaded into the sram by driving the adv pin low, i nto load mode. burst order the burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. the burst sequence is determined by the state of the linear burst order pin ( lbo ). when this pin is low, a linear burst sequence is selected. when the ram is installed with the lbo pin tied high, interleaved burst sequence is selected. see the tabl es below for details. note: there are pull-up device s on the zq, scd dp , and ft pin s and a pull-down device s on the pe and zz pin s , so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. enable/disable parity i/o pins this sram allows the user to configure the device to operate in parity i/o active (x18, x36, or x72) or in parity i/o inactive ( x16, x32, or x64) mode. holding the pe bump low or letting it float will activate the 9th i/o on each byte of the ram. grounding pe deactivates the 9th i/o of each byte, although the bit in each byte of the memory array remains active to store and recall parit y bits generated and read into the bytesafe parity circuits. mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb parity enable pe l or nc activate 9th i/o?s (x18/36 mode) h deactivate 9th i/o?s (x16/32 mode) flxdrive output impedance control zq l high drive (low impedance) h or nc low drive (high impedance)
rev: 1.00 10/2001 21/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) x16/32/64 mode ( pe = 0) read parity error output timing diagram ck address a address b address c address d address e address f d out a d out b d out c d out d d out e tkq thz tkqx tlz dq qe f l o w t h r o u g h m o d e p i p e l i n e d m o d e d out a d out b d out c d out d tkq thz tkqx tlz dq qe err a err a err c err c
rev: 1.00 10/2001 22/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) x18/x36 mode ( pe = 1) write parity error output timing diagram bpr 1999.05.18 burst counter sequences bpr 1999.05.18 sleep mode during normal operation, zz must be pulled low, either by the user or by its internal pull down resistor. when zz is pulled high , the sram will enter a power sleep mode after 2 cycles. at this time, internal state of the sram is preserved. when zz returns to low, the sram operates normally after 2 cycles of wake up time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of ck d in a d in b d in c d in d d in e tkq thz tkqx tlz dq qe f l o w t h r o u g h m o d e p i p e l i n e d m o d e tkq thz tkqx tlz dq qe d in a d in b d in c d in d d in e err a err a err c err c linear burst sequence note: the burst counter wraps to initial state on the 5th clock. i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
rev: 1.00 10/2001 23/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an asynchronous, active high input that causes the device to enter sleep mod e. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiate d until valid pending operations are completed. similarly, when exiting sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sleep mode timing diagram designing for compatibility the gsi nbt srams offer users a configurable selection between flow through mode and pipeline mode via the ft signal found on . not all vendors offer this option, however most mark as v dd or v ddq on pipelined parts and v ss on flow through parts. gsi nbt srams are fully compatible with these sockets. note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomme nded operating conditions. exposure to conditions exceeding the absolute maximum ratings, for an extended period of time, may affect reliability of this component. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0.5 to 4.6 v v ddq voltage in v ddq pins ? 0.5 to 4.6 v v ck voltage on clock input pin ? 0.5 to 6 v v i/o voltage on i/o pins ? 0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c ck zz tzzr tzzh tzzs ~ ~ ~ ~ sleep
rev: 1.00 10/2001 24/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) power supply voltage ranges parameter symbol min. typ. max. unit notes 3.3 v supply voltage v dd3 3.0 3.3 3.6 v 2.5 v supply voltage v dd2 2.3 2.5 2.7 v 3.3 v v ddq i/o supply voltage v ddq3 3.0 3.3 3.6 v 2.5 v v ddq i/o supply voltage v ddq2 2.4 2.5 2.7 v notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. v ddq3 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 1.7 ? v dd + 0.3 v 1 v dd input low voltage v il ? 0.3 ? 0.8 v 1 v ddq i/o input high voltage v ihq 1.7 ? v ddq + 0.3 v 1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.8 v 1,3 notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v. v ddq2 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 0.6*v dd ? v dd + 0.3 v 1 v dd input low voltage v il ? 0.3 ? 0.3*v dd v 1 v ddq i/o input high voltage v ihq 0.6*v dd ? v ddq + 0.3 v 1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.3*v dd v 1,3 notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v.
rev: 1.00 10/2001 25/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) note: these parameters are sample tested. notes: 1. junction temperature is a function of sram power dissipation, package thermal resistance, mounting board temperature, ambient. t emper- ature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1 recommended operating temperatures parameter symbol min. typ. max. unit notes ambient temperature (commercial range versions) t a 0 25 70 c 2 ambient temperature (industrial range versions) t a ? 40 25 85 c 2 note: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. capacitance (t a = 25 o c , f = 1 mh z , v dd = 2.5 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 6.5 7.5 pf input/output capacitance (x36/x72) c i/o v out = 0 v 6 7 pf input/output capacitance (x18) c i/o v out = 0 v 8.5 9.5 pf package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r q ja 40 c/w 1,2 junction to ambient (at 200 lfm) four r q ja 24 c/w 1,2 junction to case (top) ? r q jc 9 c/w 3 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 2.0 v 50% v dd v il
rev: 1.00 10/2001 26/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v output load fig. 1& 2 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz 4. device is deselected as defined by the truth table. dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 2 ua 2 ua zz and pe input current i in 1 v dd 3 v in 3 v ih 0 v v in v ih ? 1 ua ? 1 ua 1 ua 100 ua ft , scd, zq, dp input current i in 2 v dd 3 v in 3 v il 0 v v in v il ? 100 ua ? 1 ua 1 ua 1 ua output leakage current (x36/x72) i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output leakage current (x18) i ol output disable, v out = 0 to v dd ? 2 ua 2 ua output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh3 i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v dq vt = 1.25 v 50 w 30pf * dq 2.5 v output load 1 output load 2 225 w 225 w 5pf * * distributed test jig capacitance
rev: 1.00 10/2001 27/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) o p e r a t i n g c u r r e n t s n o t e s : 1 . i d d a n d i d d q a p p l y t o a n y c o m b i n a t i o n o f v d d 3 , v d d 2 , v d d q 3 , a n d v d d q 2 o p e r a t i o n . 2 . a l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o . p a r a m e t e r t e s t c o n d i t i o n s m o d e s y m b o l - 2 5 0 - 2 2 5 - 2 0 0 - 1 6 6 - 1 5 0 - 1 3 3 u n i t 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c o p e r a t i n g c u r r e n t 3 . 3 v d e v i c e s e l e c t e d ; a l l o t h e r i n p u t s 3 v i h o r v i l o u t p u t o p e n ( x 7 2 ) p i p e l i n e i d d i d d q 5 8 0 8 0 5 6 0 8 0 5 3 0 7 0 5 5 0 7 0 4 8 0 6 0 5 0 0 6 0 4 1 0 5 0 4 3 0 5 0 3 8 0 5 0 4 0 0 5 0 3 4 0 4 0 3 6 0 4 0 m a f l o w t h r o u g h i d d i d d q 3 1 0 4 0 3 3 0 4 0 3 4 0 4 0 3 3 0 4 0 2 7 0 3 0 2 9 0 3 0 2 7 0 3 0 2 9 0 3 0 2 7 0 3 0 2 9 0 3 0 2 0 0 2 0 2 2 0 2 0 m a ( x 3 6 ) p i p e l i n e i d d i d d q 5 2 0 4 0 5 4 0 4 0 4 7 0 4 0 4 9 0 4 0 4 3 0 3 0 4 5 0 3 0 3 7 0 3 0 3 9 0 3 0 3 4 0 3 0 3 6 0 3 0 3 1 0 2 0 3 3 0 2 0 m a f l o w t h r o u g h i d d i d d q 2 8 0 2 0 3 0 0 2 0 2 8 0 2 0 3 0 0 2 0 2 5 0 2 0 2 7 0 2 0 3 5 0 2 0 2 7 0 2 0 2 5 0 2 0 2 7 0 2 0 1 8 0 2 0 2 0 0 2 0 m a ( x 1 8 ) p i p e l i n e i d d i d d q 3 4 5 2 0 3 6 0 2 0 3 1 5 2 0 3 3 0 2 0 2 9 0 1 5 3 0 5 1 5 2 5 0 1 5 2 6 5 1 5 2 3 0 1 5 2 4 5 1 5 2 0 5 1 0 2 2 0 1 0 m a f l o w t h r o u g h i d d i d d q 2 0 0 1 0 2 1 5 1 0 2 0 0 1 0 2 1 5 1 0 1 7 5 1 0 1 9 0 1 0 1 7 5 1 0 1 9 0 1 0 1 7 5 1 0 1 9 0 1 0 1 3 5 1 0 1 5 0 1 0 m a o p e r a t i n g c u r r e n t 2 . 5 v d e v i c e s e l e c t e d ; a l l o t h e r i n p u t s 3 v i h o r v i l o u t p u t o p e n ( x 7 2 ) p i p e l i n e i d d i d d q 5 8 0 6 0 6 0 0 6 0 5 3 0 6 0 5 5 0 6 0 4 8 0 5 0 5 0 0 5 0 4 1 0 4 0 4 3 0 4 0 3 8 0 4 0 4 0 0 4 0 3 4 0 3 0 3 6 0 3 0 m a f l o w t h r o u g h i d d i d d q 3 1 0 3 0 3 3 0 3 0 3 1 0 3 0 3 3 0 3 0 2 7 0 3 0 2 9 0 3 0 2 7 0 3 0 2 9 0 3 0 2 7 0 3 0 2 9 0 3 0 2 0 0 2 0 2 2 0 2 0 m a ( x 3 6 ) p i p e l i n e i d d i d d q 5 2 0 3 0 5 4 0 3 0 4 7 0 3 0 4 9 0 3 0 4 3 0 3 0 4 5 0 3 0 3 7 0 2 0 3 9 0 2 0 3 4 0 2 0 3 6 0 2 0 3 1 0 2 0 3 3 0 2 0 m a f l o w t h r o u g h i d d i d d q 2 8 0 2 0 3 0 0 2 0 2 8 0 2 0 3 0 0 2 0 2 5 0 2 0 2 7 0 2 0 2 5 0 2 0 2 7 0 2 0 2 5 0 2 0 2 7 0 2 0 1 8 0 1 0 2 0 0 1 0 m a ( x 1 8 ) p i p e l i n e i d d i d d q 3 4 5 1 5 3 6 0 1 5 3 1 5 1 5 3 3 0 1 5 2 9 0 1 5 3 0 5 1 5 2 5 0 1 0 2 6 5 1 0 2 3 0 1 0 2 4 5 1 0 2 0 5 1 0 2 2 0 1 0 m a f l o w t h r o u g h i d d i d d q 2 0 0 1 0 2 1 5 1 0 2 0 0 1 0 2 1 5 1 0 1 7 5 1 0 1 9 0 1 0 1 7 5 1 0 1 9 0 1 0 1 7 5 1 0 1 9 0 1 0 1 3 5 5 1 5 0 5 m a s t a n d b y c u r r e n t z z 3 v d d ? 0 . 2 v ? p i p e l i n e i s b 4 0 6 0 4 0 6 0 4 0 6 0 4 0 6 0 4 0 6 0 4 0 6 0 m a f l o w t h r o u g h i s b 4 0 6 0 4 0 6 0 4 0 6 0 4 0 6 0 4 0 6 0 4 0 6 0 m a d e s e l e c t c u r r e n t d e v i c e d e s e l e c t e d ; a l l o t h e r i n p u t s 3 v i h o r v i l ? p i p e l i n e i d d 1 7 0 1 8 0 1 6 0 1 7 0 1 5 0 1 6 0 1 3 0 1 4 0 1 2 0 1 3 0 1 0 0 1 1 0 m a f l o w t h r o u g h i d d 1 2 0 1 3 0 1 2 0 1 3 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 9 0 1 0 0 m a
rev: 1.00 10/2001 28/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) ac electrical characteristics notes: 1. these parameters are sampled and are not 100% tested. 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycle, zz must meet the specified setup and hold times as specified above. parameter symbol -250 -225 -200 -166 -150 -133 unit min max min max min max min max min max min max pipeline clock cycle time tkc 4.0 ? 4.4 ? 5.0 ? 6.0 ? 6.7 ? 7.5 ? ns clock to output valid tkq ? 2.3 ? 2.5 ? 3.0 ? 3.4 ? 3.8 ? 4.0 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns flow through clock cycle time tkc 7.0 ? 7.5 ? 8.5 ? 10.0 ? 10.0 ? 15.0 ? ns clock to output valid tkq ? 6.0 ? 6.0 ? 7.5 ? 8.5 ? 10.0 ? 10.0 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? 1.5 ? 1.7 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.7 ? 2 ? ns clock to output in high-z thz 1 1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.5 1.5 3.8 1.5 4.0 ns g to output valid toe ? 2.3 ? 2.5 ? 3.2 ? 3.5 ? 3.8 ? 4.0 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 2.3 ? 2.5 ? 3.0 ? 3.5 ? 3.8 ? 4.0 ns setup time ts 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 100 ? 100 ? 100 ? 100 ? 100 ? 100 ? ns
rev: 1.00 10/2001 29/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) pipeline mode read/write cycle timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 th ts th ck cke e * adv tkh w tkl tkc ts b n a 0 ?an a1 th ts a2 a3 d(a1) d(a2) q(a3) q q(a6) th ts d d(a5) tkqlz tkq tkqhz toehz toelz tkqx tkhqz tglqv g 1 2 3 4 5 6 7 8 9 10 command write d(a1) write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect don?t care undefined dq a ?dq d th ts th ts th ts a4 a5 a6 a7 q(a4) (a4+1) (a2+1)
rev: 1.00 10/2001 30/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) pipeline mode no-op, stall and deselect timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv w bn a 0 ?an a1 a5 d(a1) q(a2) q(a3) q(a5) dq 1 2 3 4 5 6 7 8 9 10 command write d(a1) read q(a2) stall read q(a3) write d(a4) stall nop read q(a5) continue don?t care undefined d(a4) tkhqz tkqhz deselect deselect th ts a2 a3 a4 th ts th ts th ts
rev: 1.00 10/2001 31/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) flow through mode read/write cycle timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv tkh w tkl tkc b n a 0 ?an th ts a7 dq 1 2 3 4 5 6 7 8 9 10 command write d(a1) write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect don?t care undefined th ts th ts th ts th ts th ts a1 a2 a3 a4 a5 a6 d(a1) d(a2) q(a3) q q(a6) th ts d d(a5) tkqlz tkq tkqhz toehz toelz tkqx tkhqz tglqv q(a4) (a4+1) (a2+1) g
rev: 1.00 10/2001 32/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) flow through mode no-op, stall and deselect timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv w bn a 0 ?an q(a5) dq 1 2 3 4 5 6 7 8 9 10 command write d(a1) read q(a2) stall read q(a3) write d(a4) stall nop read q(a5) continue don?t care undefined d(a4) tkhqz tkqhz deselect deselect d(a1) q(a2) q(a3) a1 a5 a2 a3 a4 th ts th ts th ts
rev: 1.00 10/2001 33/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) jtag port operation due to the fact that this device is built from two die, the two jtag parts are chained together internally. the following descr ibes the behavior of each die. overview the jtag port on this ram operates in a manner that is compliant with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input interface levels scale with v dd . the jtag output drivers are powered by v ddq . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unless clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag port registers overview the various jtag registers, refered to as test access port ortap registers, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap registers is a serial shift register that captures serial input data on the rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed betwee n the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run, test/idle , or the various data register states. instructions are 3 bits long. the instruction register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while t ms is held high for five rising edges of tck. the tap controller is also reset automaticly at power-up.
rev: 1.00 10/2001 34/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed thr ough the ram?s jtag port to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o p ins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip flops (always set to a logic 1). the relationship between th e device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. sample-z, sample/preload and extest instructions can be used to activate the boundary scan register. jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. instruction register id code register boundary scan register 0 1 2 0 1 2 31 30 29 0 1 2 n 0 bypass register tdi tdo tms tck test access port (tap) controller
rev: 1.00 10/2001 35/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990; the standard (public) instructions, and device specif ic (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on this device may be used to monitor all input and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in capture-ir state the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shift-ir state the instruction register is placed between tdi and tdo. in this state the des ired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. id register contents die revision code not used i/o configuration gsi technology jedec vendor id code p r e s e n c e r e g i s t e r bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x72 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 x36 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x32 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 x16 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1
rev: 1.00 10/2001 36/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing o f other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instruc - tion register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the bou ndary scan register. boundary scan register locations are not associated with an input or i/o pin, and are loaded with the default state id entified in the boundary scan chain table at the end of this section of the datasheet. because the ram clock is independent from the tap clock ( tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metasta ble state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shift- dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register is loaded with all logic 0s. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1
rev: 1.00 10/2001 37/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) the extest command does not block or override the ram?s input pins; therefore, the ram?s internal state is still determined by i ts input pins. typically, the boundary scan register is loaded with the desired pattern of data with the sample/preload command. then the extes t command is used to output the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling ed ge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruction is selec ted, the sate of all the ram?s input and i/o pins, as well as the default values at scan register locations not associated with a pin , are trans- ferred in parallel into the boundary scan register on the rising edge of tck in the capture-dr state, the ram?s output pins driv e out the value of the boundary scan register location with which each output pin is associated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (high-z ) and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
rev: 1.00 10/2001 38/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes 3.3 v test port input high voltage v ihj3 2.0 v dd3 +0.3 v 1 3.3 v test port input low voltage v ilj3 ? 0.3 0.8 v 1 2.5 v test port input high voltage v ihj2 0.6 * v dd2 v dd2 +0.3 v 1 2.5 v test port input low voltage v ilj2 ? 0.3 0.3 * v dd2 v 1 tms, tck and tdi input leakage current i in hj ? 300 1 ua 2 tms, tck and tdi input leakage current i in lj ? 1 100 ua 3 tdo output leakage current i olj ? 1 1 ua 4 test port output high voltage v ohj 1.7 ? v 5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v 5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i ohjc = +100 ua notes: 1. include scope and jig capacitance. 2. test conditions as as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v dq v t = 1.25 v 50 w 30pf * jtag port ac test load * distributed test jig capacitance
rev: 1.00 10/2001 39/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) jtag port timing diagram jtag port ac electrical characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns ttkq tts tth ttkh ttkl tck tms tdi tdo ttkc
rev: 1.00 10/2001 40/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) notes : 1. depending on the package, some input pads of the scan chain may not be connected to any external pin. in such case: lbo = 1, zq = 1, pe = 0, sd = 0, zz = 0, ft = 1, dp = 1, and scd = 1. 2. every dq pad consists of two scan registers?d is for input capture, and q is for output capture. 3. a single register (#194) for controlling tristate of all the dq pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control is effective after jtag extest instruction is executed. 4. 1 = no connect, internally set to logic value 1 5. 0 = no connect, internally set to logic value 0 6. x = no connect, value is undefined gs8324z18/36/72 boundary scan chain order order x72 x36 x18 bump x72 x36 x18 1(tbd)
rev: 1.00 10/2001 41/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) 209 bga package drawing 14 mm x 22 mm body, 1.0 mm bump pitch, 11 x 19 bump array symbol min typ max units a 1.70 mm a1 0.40 0.50 0.60 mm ? b 0.50 0.60 0.70 mm c 0.31 0.36 0.38 mm d 21.9 22.0 22.1 mm d1 18.0 (bsc) mm e 13.9 14.0 14.1 mm e1 10.0 (bsc) mm e 1.00 (bsc) mm aaa 0.15 mm rev 1.0 a a1 c ? b e e e e 1 d1 d aaa bottom view side view
rev: 1.00 10/2001 42/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) package dimensions?119-pin pbga a b pin 1 corner k e f c t a b c d e f g h j k l m n p r t u g s d 1 2 3 4 5 6 7 package dimensions?119-pin pbga unit: mm symbol description min. nom. max a width 13.9 14.0 14.1 b length 21.9 22.0 22.1 c package height (including ball) 1.73 1.86 1.99 d ball size 0.60 0.75 0.90 e ball height 0.50 0.60 0.70 f package height (excluding balls) 1.16 1.26 1.36 g width between balls 1.27 k package height above board 0.65 0.70 0.75 r width of package between balls 7.62 s length of package between balls 20.32 t variance of ball height 0.15 bottom view r top view side view a b c d e f g h j k l m n p r t u 119-bump bga package
rev: 1.00 10/2001 43/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) ordering information for gsi synchronous nbt srams org part number 1 type package speed 2 (mhz/ns) t a 3 2m x 18 gs8324z18b-250 pipeline/flow through 119 bga 250/6 c 2m x 18 gs8324z18b-225 pipeline/flow through 119 bga 225/6.5 c 2m x 18 gs8324z18b-200 pipeline/flow through 119 bga 200/7.5 c 2m x 18 gs8324z18b-166 pipeline/flow through 119 bga 166/8.5 c 2m x 18 gs8324z18b-150 pipeline/flow through 119 bga 150/10 c 2m x 18 gs8324z18b-133 pipeline/flow through 119 bga 133/11 c 2m x 18 gs8324z18c-250 pipeline/flow through 209 bga 250/6 c 2m x 18 gs8324z18c-225 pipeline/flow through 209 bga 225/6.5 c 2m x 18 gs8324z18c-200 pipeline/flow through 209 bga 200/7.5 c 2m x 18 gs8324z18c-166 pipeline/flow through 209 bga 166/8.5 c 2m x 18 gs8324z18c-150 pipeline/flow through 209 bga 150/10 c 2m x 18 gs8324z18c-133 pipeline/flow through 209 bga 133/11 c 1m x 36 gs8324z36b-250 pipeline/flow through 119 bga 250/6 c 1m x 36 gs8324z36b-225 pipeline/flow through 119 bga 225/6.5 c 1m x 36 gs8324z36b-200 pipeline/flow through 119 bga 200/7.5 c 1m x 36 gs8324z36b-166 pipeline/flow through 119 bga 166/8.5 c 1m x 36 gs8324z36b-150 pipeline/flow through 119 bga 150/10 c 1m x 36 gs8324z36b-133 pipeline/flow through 119 bga 133/11 c 1m x 36 gs8324z36c-250 pipeline/flow through 209 bga 250/6 c 1m x 36 gs8324z36c-225 pipeline/flow through 209 bga 225/6.5 c 1m x 36 gs8324z36c-200 pipeline/flow through 209 bga 200/7.5 c 1m x 36 gs8324z36c-166 pipeline/flow through 209 bga 166/8.5 c 1m x 36 gs8324z36c-150 pipeline/flow through 209 bga 150/10 c 1m x 36 gs8324z36c-133 pipeline/flow through 209 bga 133/11 c 512k x 72 gs8324z72c-250 pipeline/flow through 209 bga 250/6 c 512k x 72 gs8324z72c-225 pipeline/flow through 209 bga 225/6.5 c 512k x 72 gs8324z72c-200 pipeline/flow through 209 bga 200/7.5 c 512k x 72 gs8324z72c-166 pipeline/flow through 209 bga 166/8.5 c 512k x 72 gs8324z72c-150 pipeline/flow through 209 bga 150/10 c notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs 8324z 18 b - 150ib . 2. the speed column indicates the cycle frequency (mhz) of the device in pipeline mode and the latency (ns) in flow through mode. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings.
rev: 1.00 10/2001 44/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) 512k x 72 gs8324z72c-133 pipeline/flow through 209 bga 133/11 c 2m x 18 gs8324z18b-250i pipeline/flow through 119 bga 250/6 i 2m x 18 GS8324Z18B-225I pipeline/flow through 119 bga 225/6.5 i 2m x 18 gs8324z18b-200i pipeline/flow through 119 bga 200/7.5 i 2m x 18 gs8324z18b-166i pipeline/flow through 119 bga 166/8.5 i 2m x 18 gs8324z18b-150i pipeline/flow through 119 bga 150/10 i 2m x 18 gs8324z18b-133i pipeline/flow through 119 bga 133/11 i 2m x 18 gs8324z18c-250i pipeline/flow through 209 bga 250/6 i 2m x 18 gs8324z18c-225i pipeline/flow through 209 bga 225/6.5 i 2m x 18 gs8324z18c-200i pipeline/flow through 209 bga 200/7.5 i 2m x 18 gs8324z18c-166i pipeline/flow through 209 bga 166/8.5 i 2m x 18 gs8324z18c-150i pipeline/flow through 209 bga 150/10 i 2m x 18 gs8324z18c-133i pipeline/flow through 209 bga 133/11 i 1m x 36 gs8324z36b-250i pipeline/flow through 119 bga 250/6 i 1m x 36 gs8324z36b-225i pipeline/flow through 119 bga 225/6.5 i 1m x 36 gs8324z36b-200i pipeline/flow through 119 bga 200/7.5 i 1m x 36 gs8324z36b-166i pipeline/flow through 119 bga 166/8.5 i 1m x 36 gs8324z36b-150i pipeline/flow through 119 bga 150/10 i 1m x 36 gs8324z36b-133i pipeline/flow through 119 bga 133/11 i 1m x 36 gs8324z36c-250i pipeline/flow through 209 bga 250/6 i 1m x 36 gs8324z36c-225i pipeline/flow through 209 bga 225/6.5 i 1m x 36 gs8324z36c-200i pipeline/flow through 209 bga 200/7.5 i 1m x 36 gs8324z36c-166i pipeline/flow through 209 bga 166/8.5 i 1m x 36 gs8324z36c-150i pipeline/flow through 209 bga 150/10 i 1m x 36 gs8324z36c-133i pipeline/flow through 209 bga 133/11 i 512k x 72 gs8324z72c-250i pipeline/flow through 209 bga 250/6 i ordering information for gsi synchronous nbt srams (continued) org part number 1 type package speed 2 (mhz/ns) t a 3 notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs 8324z 18 b - 150ib . 2. the speed column indicates the cycle frequency (mhz) of the device in pipeline mode and the latency (ns) in flow through mode. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings.
rev: 1.00 10/2001 45/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) 512k x 72 gs8324z72c-225i pipeline/flow through 209 bga 225/6.5 i 512k x 72 gs8324z72c-200i pipeline/flow through 209 bga 200/7.5 i 512k x 72 gs8324z72c-166i pipeline/flow through 209 bga 166/8.5 i 512k x 72 gs8324z72c-150i pipeline/flow through 209 bga 150/10 i 512k x 72 gs8324z72c-133i pipeline/flow through 209 bga 133/11 i ordering information for gsi synchronous nbt srams (continued) org part number 1 type package speed 2 (mhz/ns) t a 3 notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs 8324z 18 b - 150ib . 2. the speed column indicates the cycle frequency (mhz) of the device in pipeline mode and the latency (ns) in flow through mode. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings.
rev: 1.00 10/2001 46/46 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs8324z18(b/c)/gs8324z36(b/c)/gs8324z72(c) 36mb sync sram datasheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason 8324z18_r1 ? creation of new datasheet

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